
`include "common_header.verilog"

//  *************************************************************************
//  File : tsm40_txret
//  *************************************************************************
//  This program is controlled by a written license agreement.
//  Unauthorized reproduction or use is expressly prohibited. 
//  Copyright (c) 2014 MorethanIP
//  Muenchner Strasse 199, 85757 Karlsfeld, Germany
//  info@morethanip.com
//  http://www.morethanip.com
//  *************************************************************************
//  Designed by : Daniel Koehler
//  info@morethanip.com
//  *************************************************************************
//  Description : Transfer the transmitted frame timestamp back into the
//                fifo (application) clock domain to present it at the 
//                tx_ts_xxx interface.
//  Version     : $Id: tsm40_txret.v,v 1.2 2016/12/20 12:40:18 dk Exp $
//  *************************************************************************

module tsm40_txret (

   reset_tx_clk,
   tx_clk,
   tx_ts_val_int,
   tx_ts_int,
   tx_ts_id_int,
   tx_ts_frm_out_int,
   reset_ff_tx_clk,
   ff_tx_clk,
   tx_ts_val,
   tx_ts,
   tx_ts_id,
   tx_ts_frm_out);

`include "mtip_40geth_pack_package.verilog"

input   reset_tx_clk;           //   Active High reset for tx_clk domain
input   tx_clk;                 //   XGMII transmit clock      
input   tx_ts_val_int;          //   tx_ts_xxx valid indication
input   [TS_WIDTH-1:0] tx_ts_int; //   transmit timestamp
input   [TSID_WIDTH-1:0] tx_ts_id_int; //   frame identifier
input   tx_ts_frm_out_int;      //   Transmit Timestamp Frame
input   reset_ff_tx_clk;        //   Active High reset for ff_tx_clk domain
input   ff_tx_clk;              //   Transmit Local Clock        
output   tx_ts_val;             //   tx_ts_xxx valid indication
output   [TS_WIDTH-1:0] tx_ts;  //   transmit timestamp
output   [TSID_WIDTH-1:0] tx_ts_id; //   frame identifier
output   tx_ts_frm_out;         //   Transmit Timestamp Frame

// double entry push (=double registers needed)

mtip_pushdata_xsync #(.NWIDTH(TS_WIDTH+TSID_WIDTH+1)) 

        U_PUSHXSYNC (
   
        .reset_wclk     (reset_tx_clk),
        .wclk           (tx_clk),
        .din_val        (tx_ts_val_int),
        .din            ( {tx_ts_int,tx_ts_id_int,tx_ts_frm_out_int} ),
        .reset_rclk     (reset_ff_tx_clk),
        .rclk           (ff_tx_clk),
        .dout_val       (tx_ts_val),
        .dout           ( {tx_ts,tx_ts_id,tx_ts_frm_out} ));


endmodule // module tsm40_txret

